// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator // https://github.com/SystemRDL/PeakRDL-regblock module openenoc_endpoint_full_csr ( input wire clk, input wire rst, output logic s_axil_awready, input wire s_axil_awvalid, input wire [12:0] s_axil_awaddr, input wire [2:0] s_axil_awprot, output logic s_axil_wready, input wire s_axil_wvalid, input wire [31:0] s_axil_wdata, input wire [3:0]s_axil_wstrb, input wire s_axil_bready, output logic s_axil_bvalid, output logic [1:0] s_axil_bresp, output logic s_axil_arready, input wire s_axil_arvalid, input wire [12:0] s_axil_araddr, input wire [2:0] s_axil_arprot, input wire s_axil_rready, output logic s_axil_rvalid, output logic [31:0] s_axil_rdata, output logic [1:0] s_axil_rresp, input openenoc_endpoint_full_csr_pkg::openenoc_endpoint_full_csr__in_t hwif_in, output openenoc_endpoint_full_csr_pkg::openenoc_endpoint_full_csr__out_t hwif_out ); //-------------------------------------------------------------------------- // CPU Bus interface logic //-------------------------------------------------------------------------- logic cpuif_req; logic cpuif_req_is_wr; logic [12:0] cpuif_addr; logic [31:0] cpuif_wr_data; logic [31:0] cpuif_wr_biten; logic cpuif_req_stall_wr; logic cpuif_req_stall_rd; logic cpuif_rd_ack; logic cpuif_rd_err; logic [31:0] cpuif_rd_data; logic cpuif_wr_ack; logic cpuif_wr_err; // Max Outstanding Transactions: 2 logic [1:0] axil_n_in_flight; logic axil_prev_was_rd; logic axil_arvalid; logic [12:0] axil_araddr; logic axil_ar_accept; logic axil_awvalid; logic [12:0] axil_awaddr; logic axil_wvalid; logic [31:0] axil_wdata; logic [3:0] axil_wstrb; logic axil_aw_accept; logic axil_resp_acked; // Transaction request acceptance always_ff @(posedge clk) begin if(rst) begin axil_prev_was_rd <= '0; axil_arvalid <= '0; axil_araddr <= '0; axil_awvalid <= '0; axil_awaddr <= '0; axil_wvalid <= '0; axil_wdata <= '0; axil_wstrb <= '0; axil_n_in_flight <= '0; end else begin // AR* acceptance register if(axil_ar_accept) begin axil_prev_was_rd <= '1; axil_arvalid <= '0; end if(s_axil_arvalid && s_axil_arready) begin axil_arvalid <= '1; axil_araddr <= s_axil_araddr; end // AW* & W* acceptance registers if(axil_aw_accept) begin axil_prev_was_rd <= '0; axil_awvalid <= '0; axil_wvalid <= '0; end if(s_axil_awvalid && s_axil_awready) begin axil_awvalid <= '1; axil_awaddr <= s_axil_awaddr; end if(s_axil_wvalid && s_axil_wready) begin axil_wvalid <= '1; axil_wdata <= s_axil_wdata; axil_wstrb <= s_axil_wstrb; end // Keep track of in-flight transactions if((axil_ar_accept || axil_aw_accept) && !axil_resp_acked) begin axil_n_in_flight <= axil_n_in_flight + 1'b1; end else if(!(axil_ar_accept || axil_aw_accept) && axil_resp_acked) begin axil_n_in_flight <= axil_n_in_flight - 1'b1; end end end always_comb begin s_axil_arready = (!axil_arvalid || axil_ar_accept); s_axil_awready = (!axil_awvalid || axil_aw_accept); s_axil_wready = (!axil_wvalid || axil_aw_accept); end // Request dispatch always_comb begin cpuif_wr_data = axil_wdata; for(int i=0; i<4; i++) begin cpuif_wr_biten[i*8 +: 8] = {8{axil_wstrb[i]}}; end cpuif_req = '0; cpuif_req_is_wr = '0; cpuif_addr = '0; axil_ar_accept = '0; axil_aw_accept = '0; if(axil_n_in_flight < 2'd2) begin // Can safely issue more transactions without overwhelming response buffer if(axil_arvalid && !axil_prev_was_rd) begin cpuif_req = '1; cpuif_req_is_wr = '0; cpuif_addr = {axil_araddr[12:2], 2'b0}; if(!cpuif_req_stall_rd) axil_ar_accept = '1; end else if(axil_awvalid && axil_wvalid) begin cpuif_req = '1; cpuif_req_is_wr = '1; cpuif_addr = {axil_awaddr[12:2], 2'b0}; if(!cpuif_req_stall_wr) axil_aw_accept = '1; end else if(axil_arvalid) begin cpuif_req = '1; cpuif_req_is_wr = '0; cpuif_addr = {axil_araddr[12:2], 2'b0}; if(!cpuif_req_stall_rd) axil_ar_accept = '1; end end end // AXI4-Lite Response Logic logic axil_resp_buffer_is_wr[2]; logic axil_resp_buffer_err[2]; logic [31:0] axil_resp_buffer_rdata[2]; logic [1:0] axil_resp_wptr; logic [1:0] axil_resp_rptr; always_ff @(posedge clk) begin if(rst) begin for(int i=0; i<2; i++) begin axil_resp_buffer_is_wr[i] <= '0; axil_resp_buffer_err[i] <= '0; axil_resp_buffer_rdata[i] <= '0; end axil_resp_wptr <= '0; axil_resp_rptr <= '0; end else begin // Store responses in buffer until AXI response channel accepts them if(cpuif_rd_ack || cpuif_wr_ack) begin if(cpuif_rd_ack) begin axil_resp_buffer_is_wr[axil_resp_wptr[0:0]] <= '0; axil_resp_buffer_err[axil_resp_wptr[0:0]] <= cpuif_rd_err; axil_resp_buffer_rdata[axil_resp_wptr[0:0]] <= cpuif_rd_data; end else if(cpuif_wr_ack) begin axil_resp_buffer_is_wr[axil_resp_wptr[0:0]] <= '1; axil_resp_buffer_err[axil_resp_wptr[0:0]] <= cpuif_wr_err; end axil_resp_wptr <= axil_resp_wptr + 1'b1; end // Advance read pointer when acknowledged if(axil_resp_acked) begin axil_resp_rptr <= axil_resp_rptr + 1'b1; end end end always_comb begin axil_resp_acked = '0; s_axil_bvalid = '0; s_axil_rvalid = '0; if(axil_resp_rptr != axil_resp_wptr) begin if(axil_resp_buffer_is_wr[axil_resp_rptr[0:0]]) begin s_axil_bvalid = '1; if(s_axil_bready) axil_resp_acked = '1; end else begin s_axil_rvalid = '1; if(s_axil_rready) axil_resp_acked = '1; end end s_axil_rdata = axil_resp_buffer_rdata[axil_resp_rptr[0:0]]; if(axil_resp_buffer_err[axil_resp_rptr[0:0]]) begin s_axil_bresp = 2'b10; s_axil_rresp = 2'b10; end else begin s_axil_bresp = 2'b00; s_axil_rresp = 2'b00; end end logic cpuif_req_masked; logic external_pending; // Read & write latencies are balanced. Stalls not required // except if external assign cpuif_req_stall_rd = external_pending; assign cpuif_req_stall_wr = external_pending; assign cpuif_req_masked = cpuif_req & !(!cpuif_req_is_wr & cpuif_req_stall_rd) & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode //-------------------------------------------------------------------------- typedef struct { logic test_reg; logic regB; struct { logic [1:0] info; struct { logic [1:0] mac_address; logic [1:0] multicast_address; logic non_oetp_control; logic rmem_timeout; logic dma_timeout; logic dma_max_fragment_size; } conf; struct { struct { logic data; logic control; logic status; } source; struct { logic data; logic control; logic status; } sink; } axis_if; struct { struct { logic buffer_address; logic frame_length; logic command_status; logic transferred_length; } tx; struct { logic buffer_address; logic buffer_capacity; logic command_status; logic received_length; } rx; } non_oetp_dma; struct { logic control; logic event_enable; logic status; logic claim; logic complete; } irq; struct { struct { logic [1:0] mac_address; logic rmem_address; logic local_address; logic remote_address; logic size; logic dma; } entry[4]; } peers; logic rmem; } endpoint_interface; struct { logic info; logic forwarding_control; logic default_forwarding; logic forwarding_table; } switch_interface; } decoded_reg_strb_t; decoded_reg_strb_t decoded_reg_strb; logic decoded_err; logic decoded_req_is_external; logic [12:0] decoded_addr; logic decoded_req; logic decoded_req_is_wr; logic [31:0] decoded_wr_data; logic [31:0] decoded_wr_biten; always_comb begin automatic logic is_valid_addr; automatic logic is_valid_rw; automatic logic is_external; is_external = '0; is_valid_addr = '0; is_valid_rw = '0; decoded_reg_strb.test_reg = cpuif_req_masked & (cpuif_addr == 13'h0); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h0); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h0); decoded_reg_strb.regB = cpuif_req_masked & (cpuif_addr == 13'h4); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h4); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h4); decoded_reg_strb.endpoint_interface.info[0] = cpuif_req_masked & (cpuif_addr == 13'h800) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h800); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h800) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.info[1] = cpuif_req_masked & (cpuif_addr == 13'h804) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h804); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h804) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.conf.mac_address[0] = cpuif_req_masked & (cpuif_addr == 13'h820); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h820); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h820); decoded_reg_strb.endpoint_interface.conf.mac_address[1] = cpuif_req_masked & (cpuif_addr == 13'h824); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h824); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h824); decoded_reg_strb.endpoint_interface.conf.multicast_address[0] = cpuif_req_masked & (cpuif_addr == 13'h828); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h828); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h828); decoded_reg_strb.endpoint_interface.conf.multicast_address[1] = cpuif_req_masked & (cpuif_addr == 13'h82c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h82c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h82c); decoded_reg_strb.endpoint_interface.conf.non_oetp_control = cpuif_req_masked & (cpuif_addr == 13'h830); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h830); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h830); decoded_reg_strb.endpoint_interface.conf.rmem_timeout = cpuif_req_masked & (cpuif_addr == 13'h834); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h834); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h834); decoded_reg_strb.endpoint_interface.conf.dma_timeout = cpuif_req_masked & (cpuif_addr == 13'h838); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h838); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h838); decoded_reg_strb.endpoint_interface.conf.dma_max_fragment_size = cpuif_req_masked & (cpuif_addr == 13'h83c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h83c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h83c); decoded_reg_strb.endpoint_interface.axis_if.source.data = cpuif_req_masked & (cpuif_addr == 13'h840); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h840); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h840); decoded_reg_strb.endpoint_interface.axis_if.source.control = cpuif_req_masked & (cpuif_addr == 13'h844); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h844); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h844); decoded_reg_strb.endpoint_interface.axis_if.source.status = cpuif_req_masked & (cpuif_addr == 13'h848) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h848); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h848) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.axis_if.sink.data = cpuif_req_masked & (cpuif_addr == 13'h850) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h850); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h850) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.axis_if.sink.control = cpuif_req_masked & (cpuif_addr == 13'h854); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h854); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h854); decoded_reg_strb.endpoint_interface.axis_if.sink.status = cpuif_req_masked & (cpuif_addr == 13'h858) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h858); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h858) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.buffer_address = cpuif_req_masked & (cpuif_addr == 13'h860); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h860); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h860); decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.frame_length = cpuif_req_masked & (cpuif_addr == 13'h864); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h864); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h864); decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.command_status = cpuif_req_masked & (cpuif_addr == 13'h868); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h868); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h868); decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.transferred_length = cpuif_req_masked & (cpuif_addr == 13'h86c) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h86c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h86c) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.buffer_address = cpuif_req_masked & (cpuif_addr == 13'h870); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h870); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h870); decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.buffer_capacity = cpuif_req_masked & (cpuif_addr == 13'h874); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h874); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h874); decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.command_status = cpuif_req_masked & (cpuif_addr == 13'h878); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h878); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h878); decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.received_length = cpuif_req_masked & (cpuif_addr == 13'h87c) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h87c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h87c) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.irq.control = cpuif_req_masked & (cpuif_addr == 13'h880); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h880); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h880); decoded_reg_strb.endpoint_interface.irq.event_enable = cpuif_req_masked & (cpuif_addr == 13'h884); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h884); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h884); decoded_reg_strb.endpoint_interface.irq.status = cpuif_req_masked & (cpuif_addr == 13'h888) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h888); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h888) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.irq.claim = cpuif_req_masked & (cpuif_addr == 13'h88c) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h88c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h88c) & !cpuif_req_is_wr; decoded_reg_strb.endpoint_interface.irq.complete = cpuif_req_masked & (cpuif_addr == 13'h890); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h890); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h890); for(int i0=0; i0<4; i0++) begin decoded_reg_strb.endpoint_interface.peers.entry[i0].mac_address[0] = cpuif_req_masked & (cpuif_addr == 13'h900 + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h900 + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h900 + (13)'(i0) * 13'h1c); decoded_reg_strb.endpoint_interface.peers.entry[i0].mac_address[1] = cpuif_req_masked & (cpuif_addr == 13'h904 + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h904 + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h904 + (13)'(i0) * 13'h1c); decoded_reg_strb.endpoint_interface.peers.entry[i0].rmem_address = cpuif_req_masked & (cpuif_addr == 13'h908 + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h908 + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h908 + (13)'(i0) * 13'h1c); decoded_reg_strb.endpoint_interface.peers.entry[i0].local_address = cpuif_req_masked & (cpuif_addr == 13'h90c + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h90c + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h90c + (13)'(i0) * 13'h1c); decoded_reg_strb.endpoint_interface.peers.entry[i0].remote_address = cpuif_req_masked & (cpuif_addr == 13'h910 + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h910 + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h910 + (13)'(i0) * 13'h1c); decoded_reg_strb.endpoint_interface.peers.entry[i0].size = cpuif_req_masked & (cpuif_addr == 13'h914 + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h914 + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h914 + (13)'(i0) * 13'h1c); decoded_reg_strb.endpoint_interface.peers.entry[i0].dma = cpuif_req_masked & (cpuif_addr == 13'h918 + (13)'(i0) * 13'h1c); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h918 + (13)'(i0) * 13'h1c); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h918 + (13)'(i0) * 13'h1c); end decoded_reg_strb.endpoint_interface.rmem = cpuif_req_masked & (cpuif_addr >= 13'hc00) & (cpuif_addr <= 13'hc00 + 13'h3ff); is_external |= cpuif_req_masked & (cpuif_addr >= 13'hc00) & (cpuif_addr <= 13'hc00 + 13'h3ff); is_valid_addr |= cpuif_req_masked & (cpuif_addr >= 13'hc00) & (cpuif_addr <= 13'hc00 + 13'h3ff); is_valid_rw |= cpuif_req_masked & (cpuif_addr >= 13'hc00) & (cpuif_addr <= 13'hc00 + 13'h3ff); decoded_reg_strb.switch_interface.info = cpuif_req_masked & (cpuif_addr == 13'h1000) & !cpuif_req_is_wr; is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h1000); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h1000) & !cpuif_req_is_wr; decoded_reg_strb.switch_interface.forwarding_control = cpuif_req_masked & (cpuif_addr == 13'h1004); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h1004); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h1004); decoded_reg_strb.switch_interface.default_forwarding = cpuif_req_masked & (cpuif_addr == 13'h1008); is_valid_addr |= cpuif_req_masked & (cpuif_addr == 13'h1008); is_valid_rw |= cpuif_req_masked & (cpuif_addr == 13'h1008); decoded_reg_strb.switch_interface.forwarding_table = cpuif_req_masked & (cpuif_addr >= 13'h1080) & (cpuif_addr <= 13'h1080 + 13'h7f); is_external |= cpuif_req_masked & (cpuif_addr >= 13'h1080) & (cpuif_addr <= 13'h1080 + 13'h7f); is_valid_addr |= cpuif_req_masked & (cpuif_addr >= 13'h1080) & (cpuif_addr <= 13'h1080 + 13'h7f); is_valid_rw |= cpuif_req_masked & (cpuif_addr >= 13'h1080) & (cpuif_addr <= 13'h1080 + 13'h7f); decoded_err = (~is_valid_addr | (is_valid_addr & ~is_valid_rw)) & decoded_req; decoded_req_is_external = is_external; end logic external_wr_ack; logic external_rd_ack; always_ff @(posedge clk) begin if(rst) begin external_pending <= '0; end else begin if(decoded_req_is_external & ~external_wr_ack & ~external_rd_ack) external_pending <= '1; else if(external_wr_ack | external_rd_ack) external_pending <= '0; `ifndef SYNTHESIS assert_bad_ext_wr_ack: assert(!external_wr_ack || (external_pending | decoded_req_is_external)) else $error("An external wr_ack strobe was asserted when no external request was active"); assert_bad_ext_rd_ack: assert(!external_rd_ack || (external_pending | decoded_req_is_external)) else $error("An external rd_ack strobe was asserted when no external request was active"); `endif end end // Pass down signals to next stage assign decoded_addr = cpuif_addr; assign decoded_req = cpuif_req_masked; assign decoded_req_is_wr = cpuif_req_is_wr; assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- typedef struct { struct { struct { logic [31:0] next; logic load_next; } test_field; } test_reg; struct { struct { logic [7:0] next; logic load_next; } f0; struct { logic [7:0] next; logic load_next; } f1; struct { logic [7:0] next; logic load_next; } f2; struct { logic [7:0] next; logic load_next; } f3; } regB; struct { struct { struct { struct { logic [31:0] next; logic load_next; } lo_word; struct { logic [15:0] next; logic load_next; } hi_word; } mac_address; struct { struct { logic [31:0] next; logic load_next; } lo_word; struct { logic [15:0] next; logic load_next; } hi_word; } multicast_address; struct { struct { logic [1:0] next; logic load_next; } receive_mode; } non_oetp_control; struct { struct { logic [31:0] next; logic load_next; } cycles; } rmem_timeout; struct { struct { logic [31:0] next; logic load_next; } cycles; } dma_timeout; struct { struct { logic [31:0] next; logic load_next; } bytes; } dma_max_fragment_size; } conf; struct { struct { struct { struct { logic [31:0] next; logic load_next; } tdata; } data; struct { struct { logic next; logic load_next; } tvalid; struct { logic next; logic load_next; } tlast; struct { logic [3:0] next; logic load_next; } tkeep; } control; } source; struct { struct { struct { logic next; logic load_next; } tready; } control; } sink; } axis_if; struct { struct { struct { struct { logic [31:0] next; logic load_next; } base; } buffer_address; struct { struct { logic [31:0] next; logic load_next; } bytes; } frame_length; struct { struct { logic next; logic load_next; } request; struct { logic next; logic load_next; } clear_errors; } command_status; } tx; struct { struct { struct { logic [31:0] next; logic load_next; } base; } buffer_address; struct { struct { logic [31:0] next; logic load_next; } bytes; } buffer_capacity; struct { struct { logic next; logic load_next; } request; struct { logic next; logic load_next; } clear_errors; } command_status; } rx; } non_oetp_dma; struct { struct { struct { logic next; logic load_next; } global_enable; struct { logic next; logic load_next; } clear_errors; } control; struct { struct { logic next; logic load_next; } peer_dma_complete; struct { logic next; logic load_next; } non_oetp_dma_tx_complete; struct { logic next; logic load_next; } non_oetp_dma_rx_complete; struct { logic next; logic load_next; } non_oetp_direct_tx_complete; struct { logic next; logic load_next; } non_oetp_direct_rx_available; struct { logic next; logic load_next; } rmem_error; } event_enable; struct { struct { logic [10:0] next; logic load_next; } peer_idx; struct { logic [3:0] next; logic load_next; } source; struct { logic [15:0] next; logic load_next; } seq; struct { logic next; logic load_next; } valid; } complete; } irq; struct { struct { struct { struct { logic [31:0] next; logic load_next; } lo_word; struct { logic [15:0] next; logic load_next; } hi_word; } mac_address; struct { struct { logic [31:0] next; logic load_next; } offset; } rmem_address; struct { struct { logic [31:0] next; logic load_next; } base; } local_address; struct { struct { logic [31:0] next; logic load_next; } base; } remote_address; struct { struct { logic [31:0] next; logic load_next; } bytes; } size; struct { struct { logic [1:0] next; logic load_next; } mode; struct { logic next; logic load_next; } irq_enable; struct { logic next; logic load_next; } request; struct { logic next; logic load_next; } clear_error; } dma; } entry[4]; } peers; } endpoint_interface; struct { struct { struct { logic next; logic load_next; } operation_mode; struct { logic next; logic load_next; } pause_request; } forwarding_control; struct { struct { logic [3:0] next; logic load_next; } bitmap; } default_forwarding; } switch_interface; } field_combo_t; field_combo_t field_combo; typedef struct { struct { struct { logic [31:0] value; } test_field; } test_reg; struct { struct { logic [7:0] value; } f0; struct { logic [7:0] value; } f1; struct { logic [7:0] value; } f2; struct { logic [7:0] value; } f3; } regB; struct { struct { struct { struct { logic [31:0] value; } lo_word; struct { logic [15:0] value; } hi_word; } mac_address; struct { struct { logic [31:0] value; } lo_word; struct { logic [15:0] value; } hi_word; } multicast_address; struct { struct { logic [1:0] value; } receive_mode; } non_oetp_control; struct { struct { logic [31:0] value; } cycles; } rmem_timeout; struct { struct { logic [31:0] value; } cycles; } dma_timeout; struct { struct { logic [31:0] value; } bytes; } dma_max_fragment_size; } conf; struct { struct { struct { struct { logic [31:0] value; } tdata; } data; struct { struct { logic value; } tvalid; struct { logic value; } tlast; struct { logic [3:0] value; } tkeep; } control; } source; struct { struct { struct { logic value; } tready; } control; } sink; } axis_if; struct { struct { struct { struct { logic [31:0] value; } base; } buffer_address; struct { struct { logic [31:0] value; } bytes; } frame_length; struct { struct { logic value; } request; struct { logic value; } clear_errors; } command_status; } tx; struct { struct { struct { logic [31:0] value; } base; } buffer_address; struct { struct { logic [31:0] value; } bytes; } buffer_capacity; struct { struct { logic value; } request; struct { logic value; } clear_errors; } command_status; } rx; } non_oetp_dma; struct { struct { struct { logic value; } global_enable; struct { logic value; } clear_errors; } control; struct { struct { logic value; } peer_dma_complete; struct { logic value; } non_oetp_dma_tx_complete; struct { logic value; } non_oetp_dma_rx_complete; struct { logic value; } non_oetp_direct_tx_complete; struct { logic value; } non_oetp_direct_rx_available; struct { logic value; } rmem_error; } event_enable; struct { struct { logic [10:0] value; } peer_idx; struct { logic [3:0] value; } source; struct { logic [15:0] value; } seq; struct { logic value; } valid; } complete; } irq; struct { struct { struct { struct { logic [31:0] value; } lo_word; struct { logic [15:0] value; } hi_word; } mac_address; struct { struct { logic [31:0] value; } offset; } rmem_address; struct { struct { logic [31:0] value; } base; } local_address; struct { struct { logic [31:0] value; } base; } remote_address; struct { struct { logic [31:0] value; } bytes; } size; struct { struct { logic [1:0] value; } mode; struct { logic value; } irq_enable; struct { logic value; } request; struct { logic value; } clear_error; } dma; } entry[4]; } peers; } endpoint_interface; struct { struct { struct { logic value; } operation_mode; struct { logic value; } pause_request; } forwarding_control; struct { struct { logic [3:0] value; } bitmap; } default_forwarding; } switch_interface; } field_storage_t; field_storage_t field_storage; // Field: openenoc_endpoint_full_csr.test_reg.test_field always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.test_reg.test_field.value; load_next_c = '0; if(decoded_reg_strb.test_reg && decoded_req_is_wr) begin // SW write next_c = (field_storage.test_reg.test_field.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.test_reg.test_field.next = next_c; field_combo.test_reg.test_field.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.test_reg.test_field.value <= 32'h0; end else begin if(field_combo.test_reg.test_field.load_next) begin field_storage.test_reg.test_field.value <= field_combo.test_reg.test_field.next; end end end assign hwif_out.test_reg.test_field.value = field_storage.test_reg.test_field.value; // Field: openenoc_endpoint_full_csr.regB.f0 always_comb begin automatic logic [7:0] next_c; automatic logic load_next_c; next_c = field_storage.regB.f0.value; load_next_c = '0; if(decoded_reg_strb.regB && decoded_req_is_wr) begin // SW write next_c = (field_storage.regB.f0.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]); load_next_c = '1; end field_combo.regB.f0.next = next_c; field_combo.regB.f0.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.regB.f0.value <= 8'h0; end else begin if(field_combo.regB.f0.load_next) begin field_storage.regB.f0.value <= field_combo.regB.f0.next; end end end assign hwif_out.regB.f0.value = field_storage.regB.f0.value; // Field: openenoc_endpoint_full_csr.regB.f1 always_comb begin automatic logic [7:0] next_c; automatic logic load_next_c; next_c = field_storage.regB.f1.value; load_next_c = '0; if(decoded_reg_strb.regB && decoded_req_is_wr) begin // SW write next_c = (field_storage.regB.f1.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]); load_next_c = '1; end field_combo.regB.f1.next = next_c; field_combo.regB.f1.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.regB.f1.value <= 8'h0; end else begin if(field_combo.regB.f1.load_next) begin field_storage.regB.f1.value <= field_combo.regB.f1.next; end end end assign hwif_out.regB.f1.value = field_storage.regB.f1.value; // Field: openenoc_endpoint_full_csr.regB.f2 always_comb begin automatic logic [7:0] next_c; automatic logic load_next_c; next_c = field_storage.regB.f2.value; load_next_c = '0; if(decoded_reg_strb.regB && decoded_req_is_wr) begin // SW write next_c = (field_storage.regB.f2.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]); load_next_c = '1; end field_combo.regB.f2.next = next_c; field_combo.regB.f2.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.regB.f2.value <= 8'h0; end else begin if(field_combo.regB.f2.load_next) begin field_storage.regB.f2.value <= field_combo.regB.f2.next; end end end assign hwif_out.regB.f2.value = field_storage.regB.f2.value; // Field: openenoc_endpoint_full_csr.regB.f3 always_comb begin automatic logic [7:0] next_c; automatic logic load_next_c; next_c = field_storage.regB.f3.value; load_next_c = '0; if(decoded_reg_strb.regB && decoded_req_is_wr) begin // SW write next_c = (field_storage.regB.f3.value & ~decoded_wr_biten[31:24]) | (decoded_wr_data[31:24] & decoded_wr_biten[31:24]); load_next_c = '1; end field_combo.regB.f3.next = next_c; field_combo.regB.f3.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.regB.f3.value <= 8'h0; end else begin if(field_combo.regB.f3.load_next) begin field_storage.regB.f3.value <= field_combo.regB.f3.next; end end end assign hwif_out.regB.f3.value = field_storage.regB.f3.value; assign hwif_out.endpoint_interface.info.rmem_total_depth.value = 32'h100; assign hwif_out.endpoint_interface.info.num_of_peers.value = 11'h4; assign hwif_out.endpoint_interface.info.peer_dma_supported.value = 1'h1; assign hwif_out.endpoint_interface.info.non_oetp_dma_supported.value = 1'h1; assign hwif_out.endpoint_interface.info.direct_axis_supported.value = 1'h1; assign hwif_out.endpoint_interface.info.rmem_supported.value = 1'h1; assign hwif_out.endpoint_interface.info.irq_supported.value = 1'h1; assign hwif_out.endpoint_interface.info.max_dma_frame_size_bytes.value = 16'h2000; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.mac_address.lo_word always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.mac_address.lo_word.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.mac_address[0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.mac_address.lo_word.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.mac_address.lo_word.next = next_c; field_combo.endpoint_interface.conf.mac_address.lo_word.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.mac_address.lo_word.value <= 32'h0; end else begin if(field_combo.endpoint_interface.conf.mac_address.lo_word.load_next) begin field_storage.endpoint_interface.conf.mac_address.lo_word.value <= field_combo.endpoint_interface.conf.mac_address.lo_word.next; end end end assign hwif_out.endpoint_interface.conf.mac_address.lo_word.value = field_storage.endpoint_interface.conf.mac_address.lo_word.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.mac_address.hi_word always_comb begin automatic logic [15:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.mac_address.hi_word.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.mac_address[1] && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.mac_address.hi_word.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.mac_address.hi_word.next = next_c; field_combo.endpoint_interface.conf.mac_address.hi_word.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.mac_address.hi_word.value <= 16'h0; end else begin if(field_combo.endpoint_interface.conf.mac_address.hi_word.load_next) begin field_storage.endpoint_interface.conf.mac_address.hi_word.value <= field_combo.endpoint_interface.conf.mac_address.hi_word.next; end end end assign hwif_out.endpoint_interface.conf.mac_address.hi_word.value = field_storage.endpoint_interface.conf.mac_address.hi_word.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.multicast_address.lo_word always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.multicast_address.lo_word.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.multicast_address[0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.multicast_address.lo_word.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.multicast_address.lo_word.next = next_c; field_combo.endpoint_interface.conf.multicast_address.lo_word.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.multicast_address.lo_word.value <= 32'h0; end else begin if(field_combo.endpoint_interface.conf.multicast_address.lo_word.load_next) begin field_storage.endpoint_interface.conf.multicast_address.lo_word.value <= field_combo.endpoint_interface.conf.multicast_address.lo_word.next; end end end assign hwif_out.endpoint_interface.conf.multicast_address.lo_word.value = field_storage.endpoint_interface.conf.multicast_address.lo_word.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.multicast_address.hi_word always_comb begin automatic logic [15:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.multicast_address.hi_word.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.multicast_address[1] && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.multicast_address.hi_word.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.multicast_address.hi_word.next = next_c; field_combo.endpoint_interface.conf.multicast_address.hi_word.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.multicast_address.hi_word.value <= 16'h0; end else begin if(field_combo.endpoint_interface.conf.multicast_address.hi_word.load_next) begin field_storage.endpoint_interface.conf.multicast_address.hi_word.value <= field_combo.endpoint_interface.conf.multicast_address.hi_word.next; end end end assign hwif_out.endpoint_interface.conf.multicast_address.hi_word.value = field_storage.endpoint_interface.conf.multicast_address.hi_word.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.non_oetp_control.receive_mode always_comb begin automatic logic [1:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.non_oetp_control.receive_mode.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.non_oetp_control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.non_oetp_control.receive_mode.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.non_oetp_control.receive_mode.next = next_c; field_combo.endpoint_interface.conf.non_oetp_control.receive_mode.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.non_oetp_control.receive_mode.value <= 2'h1; end else begin if(field_combo.endpoint_interface.conf.non_oetp_control.receive_mode.load_next) begin field_storage.endpoint_interface.conf.non_oetp_control.receive_mode.value <= field_combo.endpoint_interface.conf.non_oetp_control.receive_mode.next; end end end assign hwif_out.endpoint_interface.conf.non_oetp_control.receive_mode.value = field_storage.endpoint_interface.conf.non_oetp_control.receive_mode.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.rmem_timeout.cycles always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.rmem_timeout.cycles.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.rmem_timeout && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.rmem_timeout.cycles.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.rmem_timeout.cycles.next = next_c; field_combo.endpoint_interface.conf.rmem_timeout.cycles.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.rmem_timeout.cycles.value <= 32'h0; end else begin if(field_combo.endpoint_interface.conf.rmem_timeout.cycles.load_next) begin field_storage.endpoint_interface.conf.rmem_timeout.cycles.value <= field_combo.endpoint_interface.conf.rmem_timeout.cycles.next; end end end assign hwif_out.endpoint_interface.conf.rmem_timeout.cycles.value = field_storage.endpoint_interface.conf.rmem_timeout.cycles.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.dma_timeout.cycles always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.dma_timeout.cycles.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.dma_timeout && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.dma_timeout.cycles.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.dma_timeout.cycles.next = next_c; field_combo.endpoint_interface.conf.dma_timeout.cycles.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.dma_timeout.cycles.value <= 32'h0; end else begin if(field_combo.endpoint_interface.conf.dma_timeout.cycles.load_next) begin field_storage.endpoint_interface.conf.dma_timeout.cycles.value <= field_combo.endpoint_interface.conf.dma_timeout.cycles.next; end end end assign hwif_out.endpoint_interface.conf.dma_timeout.cycles.value = field_storage.endpoint_interface.conf.dma_timeout.cycles.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.conf.dma_max_fragment_size.bytes always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.conf.dma_max_fragment_size.bytes.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.conf.dma_max_fragment_size && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.conf.dma_max_fragment_size.bytes.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.conf.dma_max_fragment_size.bytes.next = next_c; field_combo.endpoint_interface.conf.dma_max_fragment_size.bytes.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.conf.dma_max_fragment_size.bytes.value <= 32'h1fe0; end else begin if(field_combo.endpoint_interface.conf.dma_max_fragment_size.bytes.load_next) begin field_storage.endpoint_interface.conf.dma_max_fragment_size.bytes.value <= field_combo.endpoint_interface.conf.dma_max_fragment_size.bytes.next; end end end assign hwif_out.endpoint_interface.conf.dma_max_fragment_size.bytes.value = field_storage.endpoint_interface.conf.dma_max_fragment_size.bytes.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.axis_if.source.data.tdata always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.axis_if.source.data.tdata.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.axis_if.source.data && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.axis_if.source.data.tdata.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.axis_if.source.data.tdata.next = next_c; field_combo.endpoint_interface.axis_if.source.data.tdata.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.axis_if.source.data.tdata.value <= 32'h0; end else begin if(field_combo.endpoint_interface.axis_if.source.data.tdata.load_next) begin field_storage.endpoint_interface.axis_if.source.data.tdata.value <= field_combo.endpoint_interface.axis_if.source.data.tdata.next; end end end assign hwif_out.endpoint_interface.axis_if.source.data.tdata.value = field_storage.endpoint_interface.axis_if.source.data.tdata.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.axis_if.source.control.tvalid always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.axis_if.source.control.tvalid.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.axis_if.source.control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.axis_if.source.control.tvalid.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end else if(hwif_in.endpoint_interface.axis_if.source.control.tvalid.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.axis_if.source.control.tvalid.next = next_c; field_combo.endpoint_interface.axis_if.source.control.tvalid.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.axis_if.source.control.tvalid.value <= 1'h0; end else begin if(field_combo.endpoint_interface.axis_if.source.control.tvalid.load_next) begin field_storage.endpoint_interface.axis_if.source.control.tvalid.value <= field_combo.endpoint_interface.axis_if.source.control.tvalid.next; end end end assign hwif_out.endpoint_interface.axis_if.source.control.tvalid.value = field_storage.endpoint_interface.axis_if.source.control.tvalid.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.axis_if.source.control.tlast always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.axis_if.source.control.tlast.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.axis_if.source.control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.axis_if.source.control.tlast.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; end field_combo.endpoint_interface.axis_if.source.control.tlast.next = next_c; field_combo.endpoint_interface.axis_if.source.control.tlast.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.axis_if.source.control.tlast.value <= 1'h0; end else begin if(field_combo.endpoint_interface.axis_if.source.control.tlast.load_next) begin field_storage.endpoint_interface.axis_if.source.control.tlast.value <= field_combo.endpoint_interface.axis_if.source.control.tlast.next; end end end assign hwif_out.endpoint_interface.axis_if.source.control.tlast.value = field_storage.endpoint_interface.axis_if.source.control.tlast.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.axis_if.source.control.tkeep always_comb begin automatic logic [3:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.axis_if.source.control.tkeep.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.axis_if.source.control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.axis_if.source.control.tkeep.value & ~decoded_wr_biten[19:16]) | (decoded_wr_data[19:16] & decoded_wr_biten[19:16]); load_next_c = '1; end field_combo.endpoint_interface.axis_if.source.control.tkeep.next = next_c; field_combo.endpoint_interface.axis_if.source.control.tkeep.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.axis_if.source.control.tkeep.value <= 4'h0; end else begin if(field_combo.endpoint_interface.axis_if.source.control.tkeep.load_next) begin field_storage.endpoint_interface.axis_if.source.control.tkeep.value <= field_combo.endpoint_interface.axis_if.source.control.tkeep.next; end end end assign hwif_out.endpoint_interface.axis_if.source.control.tkeep.value = field_storage.endpoint_interface.axis_if.source.control.tkeep.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.axis_if.sink.control.tready always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.axis_if.sink.control.tready.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.axis_if.sink.control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.axis_if.sink.control.tready.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end else if(hwif_in.endpoint_interface.axis_if.sink.control.tready.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.axis_if.sink.control.tready.next = next_c; field_combo.endpoint_interface.axis_if.sink.control.tready.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.axis_if.sink.control.tready.value <= 1'h0; end else begin if(field_combo.endpoint_interface.axis_if.sink.control.tready.load_next) begin field_storage.endpoint_interface.axis_if.sink.control.tready.value <= field_combo.endpoint_interface.axis_if.sink.control.tready.next; end end end assign hwif_out.endpoint_interface.axis_if.sink.control.tready.value = field_storage.endpoint_interface.axis_if.sink.control.tready.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.tx.buffer_address.base always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.buffer_address && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.tx.buffer_address.base.next = next_c; field_combo.endpoint_interface.non_oetp_dma.tx.buffer_address.base.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value <= 32'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.tx.buffer_address.base.load_next) begin field_storage.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value <= field_combo.endpoint_interface.non_oetp_dma.tx.buffer_address.base.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value = field_storage.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.tx.frame_length.bytes always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.frame_length && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.next = next_c; field_combo.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value <= 32'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.load_next) begin field_storage.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value <= field_combo.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value = field_storage.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.tx.command_status.request always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.tx.command_status.request.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.command_status && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.tx.command_status.request.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; end else if(hwif_in.endpoint_interface.non_oetp_dma.tx.command_status.request.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.tx.command_status.request.next = next_c; field_combo.endpoint_interface.non_oetp_dma.tx.command_status.request.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.tx.command_status.request.value <= 1'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.tx.command_status.request.load_next) begin field_storage.endpoint_interface.non_oetp_dma.tx.command_status.request.value <= field_combo.endpoint_interface.non_oetp_dma.tx.command_status.request.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.tx.command_status.request.value = field_storage.endpoint_interface.non_oetp_dma.tx.command_status.request.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.tx.command_status && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; end else if(hwif_in.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.next = next_c; field_combo.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value <= 1'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.load_next) begin field_storage.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value <= field_combo.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value = field_storage.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.rx.buffer_address.base always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.buffer_address && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.rx.buffer_address.base.next = next_c; field_combo.endpoint_interface.non_oetp_dma.rx.buffer_address.base.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value <= 32'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.rx.buffer_address.base.load_next) begin field_storage.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value <= field_combo.endpoint_interface.non_oetp_dma.rx.buffer_address.base.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value = field_storage.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.buffer_capacity && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.next = next_c; field_combo.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value <= 32'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.load_next) begin field_storage.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value <= field_combo.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value = field_storage.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.rx.command_status.request always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.rx.command_status.request.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.command_status && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.rx.command_status.request.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; end else if(hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.request.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.rx.command_status.request.next = next_c; field_combo.endpoint_interface.non_oetp_dma.rx.command_status.request.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.rx.command_status.request.value <= 1'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.rx.command_status.request.load_next) begin field_storage.endpoint_interface.non_oetp_dma.rx.command_status.request.value <= field_combo.endpoint_interface.non_oetp_dma.rx.command_status.request.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.rx.command_status.request.value = field_storage.endpoint_interface.non_oetp_dma.rx.command_status.request.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.non_oetp_dma.rx.command_status && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; end else if(hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.next = next_c; field_combo.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value <= 1'h0; end else begin if(field_combo.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.load_next) begin field_storage.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value <= field_combo.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.next; end end end assign hwif_out.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value = field_storage.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.control.global_enable always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.control.global_enable.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.control.global_enable.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end field_combo.endpoint_interface.irq.control.global_enable.next = next_c; field_combo.endpoint_interface.irq.control.global_enable.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.control.global_enable.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.control.global_enable.load_next) begin field_storage.endpoint_interface.irq.control.global_enable.value <= field_combo.endpoint_interface.irq.control.global_enable.next; end end end assign hwif_out.endpoint_interface.irq.control.global_enable.value = field_storage.endpoint_interface.irq.control.global_enable.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.control.clear_errors always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.control.clear_errors.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.control && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.control.clear_errors.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; end else if(hwif_in.endpoint_interface.irq.control.clear_errors.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.irq.control.clear_errors.next = next_c; field_combo.endpoint_interface.irq.control.clear_errors.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.control.clear_errors.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.control.clear_errors.load_next) begin field_storage.endpoint_interface.irq.control.clear_errors.value <= field_combo.endpoint_interface.irq.control.clear_errors.next; end end end assign hwif_out.endpoint_interface.irq.control.clear_errors.value = field_storage.endpoint_interface.irq.control.clear_errors.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.event_enable.peer_dma_complete always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.event_enable.peer_dma_complete.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.event_enable && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.event_enable.peer_dma_complete.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end field_combo.endpoint_interface.irq.event_enable.peer_dma_complete.next = next_c; field_combo.endpoint_interface.irq.event_enable.peer_dma_complete.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.event_enable.peer_dma_complete.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.event_enable.peer_dma_complete.load_next) begin field_storage.endpoint_interface.irq.event_enable.peer_dma_complete.value <= field_combo.endpoint_interface.irq.event_enable.peer_dma_complete.next; end end end assign hwif_out.endpoint_interface.irq.event_enable.peer_dma_complete.value = field_storage.endpoint_interface.irq.event_enable.peer_dma_complete.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.event_enable && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; end field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.next = next_c; field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.load_next) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value <= field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.next; end end end assign hwif_out.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value = field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.event_enable && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; end field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.next = next_c; field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.load_next) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value <= field_combo.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.next; end end end assign hwif_out.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value = field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.event_enable && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; end field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.next = next_c; field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.load_next) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value <= field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.next; end end end assign hwif_out.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value = field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.event_enable && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; end field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.next = next_c; field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.load_next) begin field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value <= field_combo.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.next; end end end assign hwif_out.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value = field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.event_enable.rmem_error always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.event_enable.rmem_error.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.event_enable && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.event_enable.rmem_error.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; end field_combo.endpoint_interface.irq.event_enable.rmem_error.next = next_c; field_combo.endpoint_interface.irq.event_enable.rmem_error.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.event_enable.rmem_error.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.event_enable.rmem_error.load_next) begin field_storage.endpoint_interface.irq.event_enable.rmem_error.value <= field_combo.endpoint_interface.irq.event_enable.rmem_error.next; end end end assign hwif_out.endpoint_interface.irq.event_enable.rmem_error.value = field_storage.endpoint_interface.irq.event_enable.rmem_error.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.complete.peer_idx always_comb begin automatic logic [10:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.complete.peer_idx.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.complete && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.complete.peer_idx.value & ~decoded_wr_biten[10:0]) | (decoded_wr_data[10:0] & decoded_wr_biten[10:0]); load_next_c = '1; end field_combo.endpoint_interface.irq.complete.peer_idx.next = next_c; field_combo.endpoint_interface.irq.complete.peer_idx.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.complete.peer_idx.value <= 11'h0; end else begin if(field_combo.endpoint_interface.irq.complete.peer_idx.load_next) begin field_storage.endpoint_interface.irq.complete.peer_idx.value <= field_combo.endpoint_interface.irq.complete.peer_idx.next; end end end assign hwif_out.endpoint_interface.irq.complete.peer_idx.value = field_storage.endpoint_interface.irq.complete.peer_idx.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.complete.source always_comb begin automatic logic [3:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.complete.source.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.complete && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.complete.source.value & ~decoded_wr_biten[14:11]) | (decoded_wr_data[14:11] & decoded_wr_biten[14:11]); load_next_c = '1; end field_combo.endpoint_interface.irq.complete.source.next = next_c; field_combo.endpoint_interface.irq.complete.source.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.complete.source.value <= 4'h0; end else begin if(field_combo.endpoint_interface.irq.complete.source.load_next) begin field_storage.endpoint_interface.irq.complete.source.value <= field_combo.endpoint_interface.irq.complete.source.next; end end end assign hwif_out.endpoint_interface.irq.complete.source.value = field_storage.endpoint_interface.irq.complete.source.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.complete.seq always_comb begin automatic logic [15:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.complete.seq.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.complete && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.complete.seq.value & ~decoded_wr_biten[30:15]) | (decoded_wr_data[30:15] & decoded_wr_biten[30:15]); load_next_c = '1; end field_combo.endpoint_interface.irq.complete.seq.next = next_c; field_combo.endpoint_interface.irq.complete.seq.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.complete.seq.value <= 16'h0; end else begin if(field_combo.endpoint_interface.irq.complete.seq.load_next) begin field_storage.endpoint_interface.irq.complete.seq.value <= field_combo.endpoint_interface.irq.complete.seq.next; end end end assign hwif_out.endpoint_interface.irq.complete.seq.value = field_storage.endpoint_interface.irq.complete.seq.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.irq.complete.valid always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.irq.complete.valid.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.irq.complete && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.irq.complete.valid.value & ~decoded_wr_biten[31:31]) | (decoded_wr_data[31:31] & decoded_wr_biten[31:31]); load_next_c = '1; end else if(hwif_in.endpoint_interface.irq.complete.valid.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.irq.complete.valid.next = next_c; field_combo.endpoint_interface.irq.complete.valid.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.irq.complete.valid.value <= 1'h0; end else begin if(field_combo.endpoint_interface.irq.complete.valid.load_next) begin field_storage.endpoint_interface.irq.complete.valid.value <= field_combo.endpoint_interface.irq.complete.valid.next; end end end assign hwif_out.endpoint_interface.irq.complete.valid.value = field_storage.endpoint_interface.irq.complete.valid.value; for(genvar i0=0; i0<4; i0++) begin // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].mac_address.lo_word always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].mac_address.lo_word.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].mac_address[0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].mac_address.lo_word.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].mac_address.lo_word.next = next_c; field_combo.endpoint_interface.peers.entry[i0].mac_address.lo_word.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].mac_address.lo_word.load_next) begin field_storage.endpoint_interface.peers.entry[i0].mac_address.lo_word.value <= field_combo.endpoint_interface.peers.entry[i0].mac_address.lo_word.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].mac_address.lo_word.value = field_storage.endpoint_interface.peers.entry[i0].mac_address.lo_word.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].mac_address.hi_word always_comb begin automatic logic [15:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].mac_address.hi_word.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].mac_address[1] && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].mac_address.hi_word.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].mac_address.hi_word.next = next_c; field_combo.endpoint_interface.peers.entry[i0].mac_address.hi_word.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].mac_address.hi_word.load_next) begin field_storage.endpoint_interface.peers.entry[i0].mac_address.hi_word.value <= field_combo.endpoint_interface.peers.entry[i0].mac_address.hi_word.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].mac_address.hi_word.value = field_storage.endpoint_interface.peers.entry[i0].mac_address.hi_word.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].rmem_address.offset always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].rmem_address.offset.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].rmem_address && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].rmem_address.offset.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].rmem_address.offset.next = next_c; field_combo.endpoint_interface.peers.entry[i0].rmem_address.offset.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].rmem_address.offset.load_next) begin field_storage.endpoint_interface.peers.entry[i0].rmem_address.offset.value <= field_combo.endpoint_interface.peers.entry[i0].rmem_address.offset.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].rmem_address.offset.value = field_storage.endpoint_interface.peers.entry[i0].rmem_address.offset.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].local_address.base always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].local_address.base.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].local_address && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].local_address.base.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].local_address.base.next = next_c; field_combo.endpoint_interface.peers.entry[i0].local_address.base.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].local_address.base.load_next) begin field_storage.endpoint_interface.peers.entry[i0].local_address.base.value <= field_combo.endpoint_interface.peers.entry[i0].local_address.base.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].local_address.base.value = field_storage.endpoint_interface.peers.entry[i0].local_address.base.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].remote_address.base always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].remote_address.base.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].remote_address && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].remote_address.base.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].remote_address.base.next = next_c; field_combo.endpoint_interface.peers.entry[i0].remote_address.base.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].remote_address.base.load_next) begin field_storage.endpoint_interface.peers.entry[i0].remote_address.base.value <= field_combo.endpoint_interface.peers.entry[i0].remote_address.base.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].remote_address.base.value = field_storage.endpoint_interface.peers.entry[i0].remote_address.base.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].size.bytes always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].size.bytes.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].size && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].size.bytes.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].size.bytes.next = next_c; field_combo.endpoint_interface.peers.entry[i0].size.bytes.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].size.bytes.load_next) begin field_storage.endpoint_interface.peers.entry[i0].size.bytes.value <= field_combo.endpoint_interface.peers.entry[i0].size.bytes.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].size.bytes.value = field_storage.endpoint_interface.peers.entry[i0].size.bytes.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].dma.mode always_comb begin automatic logic [1:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].dma.mode.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].dma && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].dma.mode.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].dma.mode.next = next_c; field_combo.endpoint_interface.peers.entry[i0].dma.mode.load_next = load_next_c; end always_ff @(posedge clk) begin if(field_combo.endpoint_interface.peers.entry[i0].dma.mode.load_next) begin field_storage.endpoint_interface.peers.entry[i0].dma.mode.value <= field_combo.endpoint_interface.peers.entry[i0].dma.mode.next; end end assign hwif_out.endpoint_interface.peers.entry[i0].dma.mode.value = field_storage.endpoint_interface.peers.entry[i0].dma.mode.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].dma.irq_enable always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].dma.irq_enable.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].dma && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].dma.irq_enable.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].dma.irq_enable.next = next_c; field_combo.endpoint_interface.peers.entry[i0].dma.irq_enable.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.peers.entry[i0].dma.irq_enable.value <= 1'h0; end else begin if(field_combo.endpoint_interface.peers.entry[i0].dma.irq_enable.load_next) begin field_storage.endpoint_interface.peers.entry[i0].dma.irq_enable.value <= field_combo.endpoint_interface.peers.entry[i0].dma.irq_enable.next; end end end assign hwif_out.endpoint_interface.peers.entry[i0].dma.irq_enable.value = field_storage.endpoint_interface.peers.entry[i0].dma.irq_enable.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].dma.request always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].dma.request.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].dma && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].dma.request.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; end else if(hwif_in.endpoint_interface.peers.entry[i0].dma.request.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].dma.request.next = next_c; field_combo.endpoint_interface.peers.entry[i0].dma.request.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.peers.entry[i0].dma.request.value <= 1'h0; end else begin if(field_combo.endpoint_interface.peers.entry[i0].dma.request.load_next) begin field_storage.endpoint_interface.peers.entry[i0].dma.request.value <= field_combo.endpoint_interface.peers.entry[i0].dma.request.next; end end end assign hwif_out.endpoint_interface.peers.entry[i0].dma.request.value = field_storage.endpoint_interface.peers.entry[i0].dma.request.value; // Field: openenoc_endpoint_full_csr.endpoint_interface.peers.entry[].dma.clear_error always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.endpoint_interface.peers.entry[i0].dma.clear_error.value; load_next_c = '0; if(decoded_reg_strb.endpoint_interface.peers.entry[i0].dma && decoded_req_is_wr) begin // SW write next_c = (field_storage.endpoint_interface.peers.entry[i0].dma.clear_error.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; end else if(hwif_in.endpoint_interface.peers.entry[i0].dma.clear_error.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; end field_combo.endpoint_interface.peers.entry[i0].dma.clear_error.next = next_c; field_combo.endpoint_interface.peers.entry[i0].dma.clear_error.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.endpoint_interface.peers.entry[i0].dma.clear_error.value <= 1'h0; end else begin if(field_combo.endpoint_interface.peers.entry[i0].dma.clear_error.load_next) begin field_storage.endpoint_interface.peers.entry[i0].dma.clear_error.value <= field_combo.endpoint_interface.peers.entry[i0].dma.clear_error.next; end end end assign hwif_out.endpoint_interface.peers.entry[i0].dma.clear_error.value = field_storage.endpoint_interface.peers.entry[i0].dma.clear_error.value; end // External region: openenoc_endpoint_full_csr.endpoint_interface.rmem assign hwif_out.endpoint_interface.rmem.req = decoded_reg_strb.endpoint_interface.rmem; assign hwif_out.endpoint_interface.rmem.addr = decoded_addr[9:0]; assign hwif_out.endpoint_interface.rmem.req_is_wr = decoded_req_is_wr; assign hwif_out.endpoint_interface.rmem.wr_data = decoded_wr_data; assign hwif_out.endpoint_interface.rmem.wr_biten = decoded_wr_biten; assign hwif_out.switch_interface.info.table_depth.value = 16'h8; assign hwif_out.switch_interface.info.num_of_interfaces.value = 6'h4; // Field: openenoc_endpoint_full_csr.switch_interface.forwarding_control.operation_mode always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.switch_interface.forwarding_control.operation_mode.value; load_next_c = '0; if(decoded_reg_strb.switch_interface.forwarding_control && decoded_req_is_wr) begin // SW write next_c = (field_storage.switch_interface.forwarding_control.operation_mode.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end field_combo.switch_interface.forwarding_control.operation_mode.next = next_c; field_combo.switch_interface.forwarding_control.operation_mode.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.switch_interface.forwarding_control.operation_mode.value <= 1'h0; end else begin if(field_combo.switch_interface.forwarding_control.operation_mode.load_next) begin field_storage.switch_interface.forwarding_control.operation_mode.value <= field_combo.switch_interface.forwarding_control.operation_mode.next; end end end assign hwif_out.switch_interface.forwarding_control.operation_mode.value = field_storage.switch_interface.forwarding_control.operation_mode.value; // Field: openenoc_endpoint_full_csr.switch_interface.forwarding_control.pause_request always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; next_c = field_storage.switch_interface.forwarding_control.pause_request.value; load_next_c = '0; if(decoded_reg_strb.switch_interface.forwarding_control && decoded_req_is_wr) begin // SW write next_c = (field_storage.switch_interface.forwarding_control.pause_request.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; end field_combo.switch_interface.forwarding_control.pause_request.next = next_c; field_combo.switch_interface.forwarding_control.pause_request.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.switch_interface.forwarding_control.pause_request.value <= 1'h0; end else begin if(field_combo.switch_interface.forwarding_control.pause_request.load_next) begin field_storage.switch_interface.forwarding_control.pause_request.value <= field_combo.switch_interface.forwarding_control.pause_request.next; end end end assign hwif_out.switch_interface.forwarding_control.pause_request.value = field_storage.switch_interface.forwarding_control.pause_request.value; // Field: openenoc_endpoint_full_csr.switch_interface.default_forwarding.bitmap always_comb begin automatic logic [3:0] next_c; automatic logic load_next_c; next_c = field_storage.switch_interface.default_forwarding.bitmap.value; load_next_c = '0; if(decoded_reg_strb.switch_interface.default_forwarding && decoded_req_is_wr) begin // SW write next_c = (field_storage.switch_interface.default_forwarding.bitmap.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]); load_next_c = '1; end field_combo.switch_interface.default_forwarding.bitmap.next = next_c; field_combo.switch_interface.default_forwarding.bitmap.load_next = load_next_c; end always_ff @(posedge clk) begin if(rst) begin field_storage.switch_interface.default_forwarding.bitmap.value <= 4'h0; end else begin if(field_combo.switch_interface.default_forwarding.bitmap.load_next) begin field_storage.switch_interface.default_forwarding.bitmap.value <= field_combo.switch_interface.default_forwarding.bitmap.next; end end end assign hwif_out.switch_interface.default_forwarding.bitmap.value = field_storage.switch_interface.default_forwarding.bitmap.value; // External region: openenoc_endpoint_full_csr.switch_interface.forwarding_table assign hwif_out.switch_interface.forwarding_table.req = decoded_reg_strb.switch_interface.forwarding_table; assign hwif_out.switch_interface.forwarding_table.addr = decoded_addr[6:0]; assign hwif_out.switch_interface.forwarding_table.req_is_wr = decoded_req_is_wr; assign hwif_out.switch_interface.forwarding_table.wr_data = decoded_wr_data; assign hwif_out.switch_interface.forwarding_table.wr_biten = decoded_wr_biten; //-------------------------------------------------------------------------- // Write response //-------------------------------------------------------------------------- always_comb begin automatic logic wr_ack; wr_ack = '0; wr_ack |= hwif_in.endpoint_interface.rmem.wr_ack; wr_ack |= hwif_in.switch_interface.forwarding_table.wr_ack; external_wr_ack = wr_ack; end assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_req_is_external); // Writes are always granted with no error response assign cpuif_wr_err = decoded_err; //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- logic readback_external_rd_ack_c; always_comb begin automatic logic rd_ack; rd_ack = '0; rd_ack |= hwif_in.endpoint_interface.rmem.rd_ack; rd_ack |= hwif_in.switch_interface.forwarding_table.rd_ack; readback_external_rd_ack_c = rd_ack; end logic readback_external_rd_ack; assign readback_external_rd_ack = readback_external_rd_ack_c; logic [12:0] rd_mux_addr; logic [12:0] pending_rd_addr; // Hold read mux address to guarantee it is stable throughout any external accesses always_ff @(posedge clk) begin if(rst) begin pending_rd_addr <= '0; end else begin if(decoded_req) pending_rd_addr <= decoded_addr; end end assign rd_mux_addr = decoded_req ? decoded_addr : pending_rd_addr; logic readback_err; logic readback_done; logic [31:0] readback_data; always_comb begin automatic logic [31:0] readback_data_var; readback_data_var = '0; if(rd_mux_addr == 13'h0) begin readback_data_var[31:0] = field_storage.test_reg.test_field.value; end if(rd_mux_addr == 13'h4) begin readback_data_var[7:0] = field_storage.regB.f0.value; readback_data_var[15:8] = field_storage.regB.f1.value; readback_data_var[23:16] = field_storage.regB.f2.value; readback_data_var[31:24] = field_storage.regB.f3.value; end if(rd_mux_addr == 13'h800) begin readback_data_var[31:0] = 32'h100; end if(rd_mux_addr == 13'h804) begin readback_data_var[10:0] = 11'h4; readback_data_var[11:11] = 1'h1; readback_data_var[12:12] = 1'h1; readback_data_var[13:13] = 1'h1; readback_data_var[14:14] = 1'h1; readback_data_var[15:15] = 1'h1; readback_data_var[31:16] = 16'h2000; end if(rd_mux_addr == 13'h820) begin readback_data_var[31:0] = field_storage.endpoint_interface.conf.mac_address.lo_word.value; end if(rd_mux_addr == 13'h824) begin readback_data_var[15:0] = field_storage.endpoint_interface.conf.mac_address.hi_word.value; end if(rd_mux_addr == 13'h828) begin readback_data_var[31:0] = field_storage.endpoint_interface.conf.multicast_address.lo_word.value; end if(rd_mux_addr == 13'h82c) begin readback_data_var[15:0] = field_storage.endpoint_interface.conf.multicast_address.hi_word.value; end if(rd_mux_addr == 13'h830) begin readback_data_var[1:0] = field_storage.endpoint_interface.conf.non_oetp_control.receive_mode.value; end if(rd_mux_addr == 13'h834) begin readback_data_var[31:0] = field_storage.endpoint_interface.conf.rmem_timeout.cycles.value; end if(rd_mux_addr == 13'h838) begin readback_data_var[31:0] = field_storage.endpoint_interface.conf.dma_timeout.cycles.value; end if(rd_mux_addr == 13'h83c) begin readback_data_var[31:0] = field_storage.endpoint_interface.conf.dma_max_fragment_size.bytes.value; end if(rd_mux_addr == 13'h840) begin readback_data_var[31:0] = field_storage.endpoint_interface.axis_if.source.data.tdata.value; end if(rd_mux_addr == 13'h844) begin readback_data_var[0] = field_storage.endpoint_interface.axis_if.source.control.tvalid.value; readback_data_var[8] = field_storage.endpoint_interface.axis_if.source.control.tlast.value; readback_data_var[19:16] = field_storage.endpoint_interface.axis_if.source.control.tkeep.value; end if(rd_mux_addr == 13'h848) begin readback_data_var[0] = hwif_in.endpoint_interface.axis_if.source.status.tready.next; end if(rd_mux_addr == 13'h850) begin readback_data_var[31:0] = hwif_in.endpoint_interface.axis_if.sink.data.tdata.next; end if(rd_mux_addr == 13'h854) begin readback_data_var[0] = field_storage.endpoint_interface.axis_if.sink.control.tready.value; end if(rd_mux_addr == 13'h858) begin readback_data_var[0] = hwif_in.endpoint_interface.axis_if.sink.status.tvalid.next; readback_data_var[8] = hwif_in.endpoint_interface.axis_if.sink.status.tlast.next; readback_data_var[19:16] = hwif_in.endpoint_interface.axis_if.sink.status.tkeep.next; end if(rd_mux_addr == 13'h860) begin readback_data_var[31:0] = field_storage.endpoint_interface.non_oetp_dma.tx.buffer_address.base.value; end if(rd_mux_addr == 13'h864) begin readback_data_var[31:0] = field_storage.endpoint_interface.non_oetp_dma.tx.frame_length.bytes.value; end if(rd_mux_addr == 13'h868) begin readback_data_var[8] = field_storage.endpoint_interface.non_oetp_dma.tx.command_status.request.value; readback_data_var[9] = field_storage.endpoint_interface.non_oetp_dma.tx.command_status.clear_errors.value; readback_data_var[16] = hwif_in.endpoint_interface.non_oetp_dma.tx.command_status.idle.next; readback_data_var[24] = hwif_in.endpoint_interface.non_oetp_dma.tx.command_status.done.next; readback_data_var[25] = hwif_in.endpoint_interface.non_oetp_dma.tx.command_status.error.next; readback_data_var[31:28] = hwif_in.endpoint_interface.non_oetp_dma.tx.command_status.error_code.next; end if(rd_mux_addr == 13'h86c) begin readback_data_var[31:0] = hwif_in.endpoint_interface.non_oetp_dma.tx.transferred_length.bytes.next; end if(rd_mux_addr == 13'h870) begin readback_data_var[31:0] = field_storage.endpoint_interface.non_oetp_dma.rx.buffer_address.base.value; end if(rd_mux_addr == 13'h874) begin readback_data_var[31:0] = field_storage.endpoint_interface.non_oetp_dma.rx.buffer_capacity.bytes.value; end if(rd_mux_addr == 13'h878) begin readback_data_var[8] = field_storage.endpoint_interface.non_oetp_dma.rx.command_status.request.value; readback_data_var[9] = field_storage.endpoint_interface.non_oetp_dma.rx.command_status.clear_errors.value; readback_data_var[16] = hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.idle.next; readback_data_var[17] = hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.armed.next; readback_data_var[24] = hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.done.next; readback_data_var[25] = hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.error.next; readback_data_var[31:28] = hwif_in.endpoint_interface.non_oetp_dma.rx.command_status.error_code.next; end if(rd_mux_addr == 13'h87c) begin readback_data_var[31:0] = hwif_in.endpoint_interface.non_oetp_dma.rx.received_length.bytes.next; end if(rd_mux_addr == 13'h880) begin readback_data_var[0] = field_storage.endpoint_interface.irq.control.global_enable.value; readback_data_var[8] = field_storage.endpoint_interface.irq.control.clear_errors.value; end if(rd_mux_addr == 13'h884) begin readback_data_var[0] = field_storage.endpoint_interface.irq.event_enable.peer_dma_complete.value; readback_data_var[1] = field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_tx_complete.value; readback_data_var[2] = field_storage.endpoint_interface.irq.event_enable.non_oetp_dma_rx_complete.value; readback_data_var[3] = field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_tx_complete.value; readback_data_var[4] = field_storage.endpoint_interface.irq.event_enable.non_oetp_direct_rx_available.value; readback_data_var[5] = field_storage.endpoint_interface.irq.event_enable.rmem_error.value; end if(rd_mux_addr == 13'h888) begin readback_data_var[0] = hwif_in.endpoint_interface.irq.status.claim_pending.next; readback_data_var[1] = hwif_in.endpoint_interface.irq.status.credit_full.next; readback_data_var[2] = hwif_in.endpoint_interface.irq.status.overflow.next; readback_data_var[3] = hwif_in.endpoint_interface.irq.status.invalid_complete.next; readback_data_var[4] = hwif_in.endpoint_interface.irq.status.irq_asserted.next; readback_data_var[15:8] = hwif_in.endpoint_interface.irq.status.fifo_level.next; readback_data_var[23:16] = hwif_in.endpoint_interface.irq.status.reserved_count.next; end if(rd_mux_addr == 13'h88c) begin readback_data_var[10:0] = hwif_in.endpoint_interface.irq.claim.peer_idx.next; readback_data_var[14:11] = hwif_in.endpoint_interface.irq.claim.source.next; readback_data_var[30:15] = hwif_in.endpoint_interface.irq.claim.seq.next; readback_data_var[31] = hwif_in.endpoint_interface.irq.claim.valid.next; end if(rd_mux_addr == 13'h890) begin readback_data_var[10:0] = field_storage.endpoint_interface.irq.complete.peer_idx.value; readback_data_var[14:11] = field_storage.endpoint_interface.irq.complete.source.value; readback_data_var[30:15] = field_storage.endpoint_interface.irq.complete.seq.value; readback_data_var[31] = field_storage.endpoint_interface.irq.complete.valid.value; end for(int i0=0; i0<4; i0++) begin if(rd_mux_addr == 13'h900 + (13)'(i0) * 13'h1c) begin readback_data_var[31:0] = field_storage.endpoint_interface.peers.entry[i0].mac_address.lo_word.value; end if(rd_mux_addr == 13'h904 + (13)'(i0) * 13'h1c) begin readback_data_var[15:0] = field_storage.endpoint_interface.peers.entry[i0].mac_address.hi_word.value; end if(rd_mux_addr == 13'h908 + (13)'(i0) * 13'h1c) begin readback_data_var[31:0] = field_storage.endpoint_interface.peers.entry[i0].rmem_address.offset.value; end if(rd_mux_addr == 13'h90c + (13)'(i0) * 13'h1c) begin readback_data_var[31:0] = field_storage.endpoint_interface.peers.entry[i0].local_address.base.value; end if(rd_mux_addr == 13'h910 + (13)'(i0) * 13'h1c) begin readback_data_var[31:0] = field_storage.endpoint_interface.peers.entry[i0].remote_address.base.value; end if(rd_mux_addr == 13'h914 + (13)'(i0) * 13'h1c) begin readback_data_var[31:0] = field_storage.endpoint_interface.peers.entry[i0].size.bytes.value; end if(rd_mux_addr == 13'h918 + (13)'(i0) * 13'h1c) begin readback_data_var[1:0] = field_storage.endpoint_interface.peers.entry[i0].dma.mode.value; readback_data_var[2] = field_storage.endpoint_interface.peers.entry[i0].dma.irq_enable.value; readback_data_var[8] = field_storage.endpoint_interface.peers.entry[i0].dma.request.value; readback_data_var[9] = field_storage.endpoint_interface.peers.entry[i0].dma.clear_error.value; readback_data_var[16] = hwif_in.endpoint_interface.peers.entry[i0].dma.idle.next; readback_data_var[24] = hwif_in.endpoint_interface.peers.entry[i0].dma.done.next; readback_data_var[25] = hwif_in.endpoint_interface.peers.entry[i0].dma.error.next; readback_data_var[31:28] = hwif_in.endpoint_interface.peers.entry[i0].dma.error_code.next; end end if((rd_mux_addr >= 13'hc00) && (rd_mux_addr <= 13'hc00 + 13'h3ff)) begin readback_data_var = hwif_in.endpoint_interface.rmem.rd_data; end if(rd_mux_addr == 13'h1000) begin readback_data_var[15:0] = 16'h8; readback_data_var[21:16] = 6'h4; end if(rd_mux_addr == 13'h1004) begin readback_data_var[0] = field_storage.switch_interface.forwarding_control.operation_mode.value; readback_data_var[7] = field_storage.switch_interface.forwarding_control.pause_request.value; readback_data_var[15] = hwif_in.switch_interface.forwarding_control.pause_done.next; end if(rd_mux_addr == 13'h1008) begin readback_data_var[3:0] = field_storage.switch_interface.default_forwarding.bitmap.value; end if((rd_mux_addr >= 13'h1080) && (rd_mux_addr <= 13'h1080 + 13'h7f)) begin readback_data_var = hwif_in.switch_interface.forwarding_table.rd_data; end readback_data = readback_data_var; readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_req_is_external; readback_err = decoded_err; end assign external_rd_ack = readback_external_rd_ack; assign cpuif_rd_ack = readback_done | readback_external_rd_ack; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; endmodule