Control and status address map for an openENOC Endpoint Interface instance.

Control and status register file for an openENOC Endpoint Interface instance.

Read-only information register for this openENOC Endpoint Interface instance.

Total depth of the shared memory region for all remote peers. This field reflects the RMEM_TOTAL_DEPTH parameter value.

Number of remote peers supported by this openENOC Endpoint Interface instance, from 0 to 2047. This field reflects the NUM_OF_PEERS parameter value.

Indicates whether DMA transfers associated with configured remote peers are supported.

Indicates whether endpoint-level DMA transfers of complete non-oETP Ethernet frames are supported.

Indicates whether direct CSR-driven AXI4-Stream access is supported for non-oETP Ethernet frames.

Indicates whether the transparent Remote Memory (RMEM) interface is supported.

Indicates whether the endpoint interrupt output and interrupt-control logic are implemented.

Synthesis-time maximum Ethernet frame size in bytes, excluding FCS. This field reflects the MAX_RAW_FRAME_SIZE parameter value and bounds raw non-oETP DMA frames. The peer DMA memory-fragment ceiling is 4 * floor((MAX_RAW_FRAME_SIZE - 32) / 4), accounting for the Ethernet header, oETP write metadata, data-word padding and EndOfData. An 8192-byte frame limit permits 8160-byte memory fragments. A value of zero indicates that DMA is not supported.

Configuration register file for this openENOC Endpoint Interface instance.

Local endpoint 48-bit unicast MAC address. The oETP engine uses this address as its source MAC and compares individual-addressed incoming oETP frames against it. The I/G bit in the first MAC octet must be zero. Group-addressed oETP frames are compared against conf.multicast_address instead.

Lower 32 bits [31:0] of the 48-bit MAC address.

Upper 16 bits [47:32] of the 48-bit MAC address.

Local endpoint 48-bit multicast destination MAC address. For an incoming oETP frame whose destination I/G bit is one, the engine accepts the destination only when it exactly matches this address. All slave endpoints in a replication group use the same value. This address is not used as a source MAC. Zero is the reset value and matches no group-addressed destination, disabling oETP group reception. Broadcast is accepted only when this address is all ones. This field does not change the separate non-oETP receive-mode policy.

Lower 32 bits [31:0] of the 48-bit multicast MAC address.

Upper 16 bits [47:32] of the 48-bit multicast MAC address.

Receive policy for Ethernet frames that do not carry oETP traffic.

Receive mode for non-oETP Ethernet frames:

• 0: Drop all non-oETP Ethernet frames.
• 1: Filtered mode. Accept frames addressed to the configured local MAC address and Ethernet broadcast frames.
• 2: Multicast mode. Accept the same frames as filtered mode, plus all multicast-addressed frames.
• 3: Promiscuous mode. Accept all non-oETP Ethernet frames.

Timeout configuration for transparent RMEM operations.

Maximum wait for an RMEM response in endpoint clock cycles. Zero disables the timeout and permits an indefinite response wait. Hardware samples this value when it accepts an RMEM operation; subsequent writes apply to later operations. The response timer starts after the complete request frame has been accepted by the Ethernet-facing transmit stream and runs until the complete matching response is received and validated through Ethernet TLAST. RX backpressure counts toward the timeout; remaining local memory completion does not. A valid response completing on the expiry edge takes priority, including a valid ERROR_RSP with its reported cause. Hardware does not retry; timeout handling and retry policy belong to software. Multicast writes do not wait for a response and do not use this response timeout. An RMEM read timeout terminates the access with all-ones read data and read ACK; a write timeout terminates with write ACK. The external-RMEM boundary uses no ERR signals. Failures set error and error_code in the associated peers.entry[].dma register and may generate a separate RMEM_ERROR IRQ event.

Common response timeout for locally initiated unicast peer DMA fragments.

Maximum wait for a response to one peer DMA fragment, in endpoint clock cycles. This value is shared by all peers. Zero disables the timeout and permits an indefinite response wait. Hardware samples this value when the oETP engine accepts the fragment request; later writes apply to later fragments. The response timer starts after the complete request frame has been accepted by the Ethernet-facing transmit stream and runs until the complete matching response is received and validated through Ethernet TLAST, including EndOfData where present. RX backpressure counts toward the timeout; remaining local memory completion does not. A valid response completing on the expiry edge takes priority, including a valid ERROR_RSP with its reported cause. On expiry, hardware aborts the remaining fragments of that DMA transfer and reports error code 8 (timeout) in the peer DMA status. Hardware does not retry; software decides whether to start another transfer. This timeout does not apply to multicast writes, non-oETP DMA, or transparent RMEM operations.

Common software-selected maximum memory fragment size for locally initiated peer DMA transfers. The synthesis-time frame limit remains fixed.

Maximum meaningful memory bytes in one locally initiated DMA fragment, excluding Ethernet/oETP headers, word padding, EndOfData and FCS. The hardware rounds the written value down to a multiple of four before validating it. The effective MFS must be at least four bytes and at most 4 * floor((MAX_RAW_FRAME_SIZE - 32) / 4). With an 8192-byte frame ceiling, the effective range is 4 through 8160 bytes in steps of four, with reset value 8160. For example, 31 selects 28, 7 selects 4, and 8161 through 8163 select 8160. Hardware snapshots the effective value when it accepts the whole peer DMA transfer; later writes apply only to subsequent transfers. The final fragment uses the exact remaining byte length and may be shorter than four bytes. A written value of 0 through 3, or a rounded value above the synthesized ceiling, rejects a new transfer with local error code 1 before issuing any memory or protocol operation. The CSR retains the unrounded written value. This setting does not restrict received peer requests, which use the synthesized fragment ceiling, and does not affect RMEM, direct CSR streams or non-oETP DMA.

Register file for the AXI4-Stream source and sink interfaces.

Register file for the AXI4-Stream source interface.

Data register for the AXI4-Stream source interface.

32-bit data value for the AXI4-Stream source interface.

Control register for the AXI4-Stream source interface.

Indicates that the AXI4-Stream source interface has valid data to send. Once asserted by software, the field remains asserted until the transfer is accepted by the destination.

Indicates the last data word of a frame on the AXI4-Stream source interface.

Indicates which byte lanes contain valid data on the AXI4-Stream source interface.

Status register for the AXI4-Stream source interface.

Registered readiness at the input of the direct TX AXI4-Stream register slice. With the non_oetp_direct_tx_complete event disabled, follows downstream backpressure through the slice's registered READY path; CSR acknowledgements and frame boundaries do not force it low. With the event enabled, additionally requires frame admission, which reserves space for the TX completion event. Acceptance of the final word (tlast) into the slice deasserts this field until the next frame receives admission. Writing the first word and setting source.control.tvalid requests admission even while this field is low. The active frame retains its admission decision if event_enable changes. Software must retain data, KEEP and LAST until source.control.tvalid is cleared by hardware, independently of this readiness status.

Register file for the AXI4-Stream sink interface.

Data register for the AXI4-Stream sink interface.

32-bit data value for the AXI4-Stream sink interface.

Control register for the AXI4-Stream sink interface.

Indicates that the AXI4-Stream sink interface is ready to accept a data transfer. Once asserted by software, the field remains asserted until a transfer occurs.

Status register for the AXI4-Stream sink interface.

Indicates that the AXI4-Stream sink interface has valid data to receive.

Indicates the last data word of a frame on the AXI4-Stream sink interface.

Indicates which byte lanes contain valid data on the AXI4-Stream sink interface.

Endpoint-level DMA control and status for complete non-oETP Ethernet frames. Frame data includes the Ethernet header and payload, but excludes the preamble, Start Frame Delimiter (SFD), and Frame Check Sequence (FCS).

Transmit DMA channel for complete non-oETP Ethernet frames.

Local memory address of the non-oETP Ethernet frame to transmit.

32-bit byte address of the first byte of the transmit buffer.

Length of the complete non-oETP Ethernet frame to transmit.

Frame length in bytes. Valid non-zero values shall not exceed info.max_dma_frame_size_bytes.

Command and completion status for the non-oETP transmit DMA channel.

Writing one requests transmission of the configured frame. The field remains asserted until the DMA engine accepts the request. Hardware clears it upon acceptance; while the channel is busy, a newly asserted request remains pending. Software or an RTL controller shall read the completion status and transferred length of the previous request before asserting this field for the next request.

Writing one clears this channel's error flag and error code. Hardware clears the command after accepting it. The command does not abort an active transfer, clear done or transferred length, or complete an IRQ claim. A new failure takes precedence over a simultaneous clear. Starting or successfully completing a transfer preserves a recorded error.

Indicates that the channel has no accepted transfer in progress. Hardware deasserts this field when a request is accepted and asserts it when the transfer completes.

Sticky successful-completion flag. Hardware sets this field after the accepted transfer completes successfully and clears it when the next request is accepted.

Sticky error-completion flag. Hardware sets this field when an accepted transfer fails. Only command_status.clear_errors or endpoint reset clears it; starting or successfully completing another transfer preserves a recorded error.

Sticky error code for the most recent transmit failure:

• 0: No error.
• 1: Invalid DMA configuration or descriptor.
• 2: AXI4-Stream length or TLAST error.
• 3: Frame exceeds the supported size or configured buffer capacity.
• 4: AXI read SLVERR response.
• 5: AXI read DECERR response.
• 6: AXI write SLVERR response.
• 7: AXI write DECERR response.
• 8-15: Reserved.

Number of bytes transferred for the most recently accepted transmit request.

Actual number of bytes transferred. Hardware clears this field when the next request is accepted.

Receive DMA channel for complete non-oETP Ethernet frames.

Local memory address of the receive buffer for a non-oETP Ethernet frame.

32-bit byte address of the first byte of the receive buffer.

Capacity of the receive buffer for one complete non-oETP Ethernet frame.

Receive-buffer capacity in bytes. Valid non-zero values shall not exceed info.max_dma_frame_size_bytes.

Command and completion status for the non-oETP receive DMA channel.

Writing one arms reception into the configured buffer. The field remains asserted until the DMA engine accepts the request. Hardware clears it upon acceptance; while the channel is busy, a newly asserted request remains pending. Software or an RTL controller shall read the completion status and received length of the previous request before asserting this field for the next request.

Writing one clears this channel's error flag and error code. Hardware clears the command after accepting it. The command does not abort an active or armed receive, clear done or received length, or complete an IRQ claim. A new failure takes precedence over a simultaneous clear. Starting or successfully completing a transfer preserves a recorded error.

Indicates that the channel has no accepted receive request in progress. After acceptance, the channel may be armed and waiting for an eligible non-oETP frame or may be writing a received frame to memory.

Indicates that the accepted receive request is waiting for an eligible non-oETP Ethernet frame. Hardware sets this field when it accepts a request and clears it when the first beat of the selected frame is accepted by the RX DMA datapath. The frame-routing logic uses this field to select the RX DMA path; otherwise an accepted non-oETP frame is directed to the CSR AXI4-Stream sink.

Sticky successful-completion flag. Hardware sets this field after a received frame has been written successfully and clears it when the next request is accepted.

Sticky error-completion flag. Hardware sets this field when an accepted receive fails. Only command_status.clear_errors or endpoint reset clears it; starting or successfully completing another receive preserves a recorded error.

Sticky error code for the most recent receive failure:

• 0: No error.
• 1: Invalid DMA configuration or descriptor.
• 2: AXI4-Stream length or TLAST error.
• 3: Received frame exceeds the configured buffer capacity.
• 4: AXI read SLVERR response.
• 5: AXI read DECERR response.
• 6: AXI write SLVERR response.
• 7: AXI write DECERR response.
• 8-15: Reserved.

Length of the most recently received non-oETP Ethernet frame.

Actual number of frame bytes written to the receive buffer. Hardware clears this field when the next request is accepted.

Endpoint-level interrupt control and claim interface. Interrupt events from peer DMA, non-oETP DMA, direct AXI4-Stream transfers, and RMEM failures are serialized through a shared event FIFO.

Global interrupt-output control and interrupt-controller maintenance requests.

Enables the physical endpoint IRQ output. Clearing this field masks the output but does not prevent enabled events from being queued. Event capture is controlled by irq.event_enable and, for peer DMA, by the selected peer's dma.irq_enable field.

Writing one requests clearing of the sticky irq.status.overflow and irq.status.invalid_complete flags. The field remains asserted until hardware accepts the request and clears it.

Enables generation of individual endpoint IRQ event classes. These fields control event capture; irq.control.global_enable only masks the physical IRQ output.

Enables PEER_DMA_COMPLETE events. A peer event is queued only when this field and the selected peer's dma.irq_enable field were both set when the DMA request was accepted. A failed incoming bulk DMA request also generates this event for the peer resolved from the source MAC. For incoming failures, hardware captures the per-peer enable when recording the failure and samples this field at IRQ admission. Successful incoming requests generate no event. CSR error recording and the error response do not wait for IRQ FIFO capacity.

Enables NON_OETP_DMA_TX_COMPLETE events. Hardware samples this field when it accepts a non-oETP transmit DMA request.

Enables NON_OETP_DMA_RX_COMPLETE events. Hardware samples this field when it accepts a non-oETP receive DMA request.

Enables NON_OETP_DIRECT_TX_COMPLETE events. Hardware samples this field when the first beat of a direct transmit frame is accepted from the CSR-facing AXI4-Stream interface. When enabled, the frame start is accepted only after an IRQ FIFO credit has been reserved. The event is generated when the final beat is accepted by the oETP engine.

Enables NON_OETP_DIRECT_RX_AVAILABLE events. One event is generated when the first beat of a new direct receive frame becomes valid on the CSR-facing AXI4-Stream interface. When enabled, routing logic does not expose that first TVALID until an IRQ FIFO credit is available, so the event cannot be lost. The event does not depend on TLAST and therefore supports both cut-through and frame-FIFO operation.

Enables RMEM_ERROR events for locally initiated RMEM failures, including timeout and an accepted ERROR_RSP, and failed incoming RMEM requests from a resolved peer. Hardware records the associated peer's dma.error and dma.error_code before exposing the event and terminates the failed RMEM access without waiting for IRQ FIFO capacity. For locally initiated failures the enable is sampled when the failure is recorded; incoming failures sample it at IRQ admission. The bulk DMA per-peer irq_enable does not gate RMEM_ERROR. Successful RMEM accesses generate no event.

Status of the endpoint IRQ event FIFO and its reservation mechanism.

Indicates that at least one valid event is available in irq.claim.

Indicates that all event FIFO credits are occupied by queued claims or reserved for admitted operations. While no credit is available, new interrupt-enabled DMA requests are not accepted and the start of an interrupt-enabled direct AXI4-Stream frame is backpressured.

Sticky internal-error flag indicating that an enabled event could not be retained. Correct credit reservation, admission control, and AXI4-Stream backpressure make this condition unreachable during normal operation. Clear with irq.control.clear_errors.

Sticky protocol-error flag indicating that irq.complete.valid was accepted while no claim was pending or that the completion token did not match the current claim. No claim is removed on a mismatch. Clear with irq.control.clear_errors.

Reflects the current value of the physical endpoint IRQ output after application of irq.control.global_enable.

Number of valid claims currently queued in the IRQ event FIFO. Values greater than 255 are reported as 255.

Number of event FIFO credits reserved for admitted DMA operations or direct transmit frames whose events have not yet been queued. Values greater than 255 are reported as 255.

Read-only view of the event at the head of the IRQ event FIFO. Reading this register has no side effect, and all fields remain stable until a matching irq.complete request removes the claim.

Zero-based peer index for a PEER_DMA_COMPLETE or RMEM_ERROR event, in the range 0 through NUM_OF_PEERS-1. The field is not applicable to other event sources and is driven to zero for deterministic readback.

IRQ event source:

• 0: PEER_DMA_COMPLETE. A peer DMA request completed with either success or error; peer_idx identifies the peer.
• 1: NON_OETP_DMA_TX_COMPLETE. A non-oETP transmit DMA request completed with either success or error.
• 2: NON_OETP_DMA_RX_COMPLETE. A non-oETP receive DMA request completed with either success or error.
• 3: NON_OETP_DIRECT_TX_COMPLETE. The final beat of a direct non-oETP transmit frame was accepted by the oETP engine.
• 4: NON_OETP_DIRECT_RX_AVAILABLE. The first beat of a new direct non-oETP receive frame is available on the CSR-facing AXI4-Stream interface.
• 5: RMEM_ERROR. A locally initiated RMEM operation failed. The cause is recorded in peers.entry[peer_idx].dma; peer_idx identifies the associated peer.
• 6-15: Reserved.

Monotonically increasing event sequence number, modulo 65536. The sequence number distinguishes otherwise identical claims and protects against stale or repeated completion requests.

Indicates that this register contains the valid event at the head of the IRQ event FIFO. When clear, all other claim fields shall be ignored.

Completion request for the current IRQ claim. Software acknowledges an event by copying the complete 32-bit irq.claim value into this register.

Peer-index portion of the claim token.

Event-source portion of the claim token.

Sequence-number portion of the claim token.

Writing one submits the completion token. The field remains asserted until hardware validates the token and clears it. A matching token removes the current claim and releases its FIFO credit; an invalid token leaves the claim unchanged and sets irq.status.invalid_complete.

Register file for remote peer configuration and memory region information.

Register file for a single remote peer configuration and memory region information.

Remote peer 48-bit destination MAC address.

Lower 32 bits [31:0] of the 48-bit MAC address.

Upper 16 bits [47:32] of the 48-bit MAC address.

Address offset of the virtual memory region corresponding to the remote peer's memory.

32-bit byte offset of the virtual memory region corresponding to the remote peer's memory. The value shall be aligned to a 32-bit word boundary.

Start address of the local memory region for DMA transfers.

Word-aligned 32-bit start address of the local memory region for DMA transfers.

Start address of the remote peer's memory region.

Word-aligned 32-bit start address of the remote peer's memory region.

Size of the remote peer's memory region.

32-bit size of the remote peer's memory region in bytes.

DMA/RMEM configuration and control for the remote peer, with shared sticky error reporting. RMEM and bulk DMA retain separate IRQ event classes.

DMA mode and responder access policy for the remote peer:

• 0: Disabled. Locally initiated DMA and transparent RMEM operations are disabled, and incoming oETP memory requests from this peer are rejected.
• 1: Transparent RMEM mode. Accesses to the virtual RMEM region are translated into individual remote memory accesses. Incoming transparent RMEM read and write requests from this peer are permitted. Bulk DMA read and write requests are rejected.
• 2: Mirror-to-local mode. A locally initiated DMA request fetches the remote memory region into the configured local memory region using remote DMA reads. On the responder side, incoming bulk DMA write requests from this peer are permitted and target the configured local memory region. Incoming bulk DMA read requests are rejected.
• 3: Mirror-to-remote mode. A locally initiated DMA request sends the configured local memory region to the remote memory region using remote DMA writes. On the responder side, incoming bulk DMA read requests from this peer are permitted and source data from the configured local memory region. Incoming bulk DMA write requests are rejected.

Consequently, a mirror relationship uses complementary modes: an initiator operating in mirror-to-local mode communicates with a responder entry configured as mirror-to-remote, while an initiator operating in mirror-to-remote mode communicates with a responder entry configured as mirror-to-local.

Enables generation of a PEER_DMA_COMPLETE IRQ event for this peer. Hardware samples this field together with irq.event_enable.peer_dma_complete when it accepts the peer DMA request. Changing the field while a transfer is active does not affect that transfer. Disabling the field does not affect DMA execution or the done, error, and error_code status fields. For a failed incoming bulk DMA request, this field is captured when recording the failure and irq.event_enable.peer_dma_complete is sampled at IRQ admission. The event identifies this peer by the received source MAC. Successful incoming requests generate no event. RMEM errors use their separate irq.event_enable.rmem_error path.

Writing one requests a DMA transfer to or from the remote peer, according to dma.mode. The field remains asserted until the DMA engine accepts and snapshots the request. Hardware clears it upon acceptance; while a transfer for this peer is active, a newly asserted request remains pending. Software or an RTL controller shall read the completion status of the previous request before asserting this field for the next request and shall keep the peer configuration stable while this field is asserted.

Writing one clears this peer's shared RMEM/DMA error flag and error code. The field remains asserted until hardware accepts and clears the command. It does not abort an active operation, clear done, or complete an IRQ claim. A new failure takes precedence over a simultaneous clear. Starting or successfully completing an operation does not clear a previously recorded error.

Indicates whether this peer has no accepted DMA request in progress. Hardware deasserts this field when a request is accepted and asserts it after all fragments of the requested block have completed.

Sticky successful-completion flag for this peer. Hardware sets this field after all fragments of the accepted block transfer complete successfully and clears it when the next request is accepted.

Shared sticky RMEM/DMA error flag for this peer. Hardware sets this field when a locally initiated RMEM access or bulk DMA transfer fails, or when servicing an incoming RMEM or bulk DMA request from this peer fails. Received requests are associated by source MAC. An incoming failure records its code before exposing its error response, independently of IRQ enable; it does not change the locally initiated dma.request, idle, or done state. An incomplete incoming DMA data frame records remote stream code 10. Multicast response suppression does not suppress this local error record or an enabled event. Only dma.clear_error or endpoint reset clears a latched error; starting or successfully completing another operation does not clear it. The flag is independent of the IRQ event-enable fields.

Shared sticky code for the most recent RMEM or bulk DMA failure for this peer:

• 0: No error.
• 1: Local invalid request, configuration, descriptor, or parameters.
• 2: Local stream/PDU length or TLAST error.
• 3: Local supported-size or buffer-capacity overflow.
• 4: Local AXI read SLVERR response.
• 5: Local AXI read DECERR response.
• 6: Local AXI write SLVERR response.
• 7: Local AXI write DECERR response.
• 8: Local peer response timeout or Request ID wrap collision. An RMEM access terminates through its ACK-only boundary; a bulk DMA timeout aborts the remaining fragments. Hardware does not retry.
• 9: Remote invalid request, configuration, descriptor, or parameters.
• 10: Remote stream/PDU length or TLAST error. Also used directly by the receiver of an incomplete DMA_WRITE_REQ or DMA_READ_RSP, including missing or incorrect EndOfData.
• 11: Remote supported-size or buffer-capacity overflow.
• 12: Remote AXI read SLVERR response.
• 13: Remote AXI read DECERR response.
• 14: Remote AXI write SLVERR response.
• 15: Remote AXI write DECERR response.

Virtual memory region for all remote peers, with offsets and sizes defined in the peers regfile.

32-bit word in the virtual memory region.

Data stored in this virtual memory word.