openENOC

Scalable Ethernet-based Network-on-Chip

openENOC is an open-source hardware and software initiative that develops a modular and scalable Ethernet-based Network-on-Chip (NoC) architecture for FPGA SoCs and advanced MPSoC designs.

Documentation

• Project Overview
  • Introduction
  • Repository Structure
  • Project Plan
  • License
  • Acknowledgements
• System Architecture
  • Introduction
  • openENOC Switch
  • openENOC Control Interface
  • openENOC Endpoint Interface
  • openENOC Transport Protocol
  • Architectural Relationships
  • Example Configurations
  • Development and Integration Flow
  • Summary
  • References
• HAL Architecture Specification
  • Introduction
  • CSR Specification Methodology
  • openENOC Switch HAL Architecture
  • openENOC Endpoint Interface HAL Architecture
  • Summary
• Verification Infrastructure
  • Introduction
  • Verification Architecture
  • Verification Framework
  • Verification Roadmap
  • Summary

Future Sections

The documentation will evolve alongside the project and gradually expand into a complete set of architectural, implementation, software, verification, and deployment resources:

• RTL Reference — Detailed documentation of RTL modules, datapaths, interfaces, and integration patterns (DOC2)

• Runtime API Reference — Software APIs, runtime services, DMA operations, and application-facing interfaces (SW3)

• Developer Guide — Tutorials, software usage, simulation workflows, FPGA deployment procedures, and reference applications (DOC3, SW2, SW4)

• Reproducibility Guide — Build environments, synthesis and place-and-route flows, automated testing, CI infrastructure, and reproducible implementation workflows (DOC4, PNR1, PNR2)

• Demo Platforms — Reference FPGA systems, educational kits, and demonstration configurations (DEM1, DEM2)

Indices

• Index

• Search Page