Switch CSR/core interface – openenoc_switch_if
Defines the structured configuration and status boundary for switch hardware and its register bank.
Source: openenoc_switch_if.sv.
RDL: openenoc_switch_interface.rdl.
Parameters
Name |
Default value |
Allowed values |
Description |
|---|---|---|---|
|
|
1..32 |
Port count and forwarding-bitmap width. |
|
|
Integer >= 1 |
Number of forwarding-table entries. |
Signals
Directions are relative to the named modport. The monitor modport, where present, observes signals as inputs and does not drive them.
Name |
Type |
Direction / role |
Description |
|---|---|---|---|
|
|
input |
Clock for this component or interface domain. |
|
|
input |
Active-high reset of transaction and control state. |
|
|
csr: input; core: output |
Hardware status, next-value updates, acknowledgements, and command clears. |
|
|
csr: output; core: input |
Stored software configuration, pending commands, and external register requests. |
Architecture and operation
The csr and core modports connect forwarding control, pause handshake,
default forwarding bitmap, and external forwarding-table CPUIF signals.
TABLE_DEPTH and NUM_OF_INTERFACES determine the table aperture and
port-bitmap width. The switch consumes the core view; the endpoint’s
generated bridge drives the csr view.
Shared-bus and crossbar switches use the same configuration and status fields:
forwarding_control.operation_mode selects managed or unmanaged operation,
default_forwarding.bitmap supplies the destination set for a table miss,
and forwarding_table exposes one common table through CPUIF. Table entries
and the default route both use egress-port bitmaps, including multicast sets.
forwarding_control.pause_request and pause_done coordinate forwarding
pause. Arbitration of the crossbar’s per-ingress lookup and learning requests
is internal and adds no per-engine software table or control port.
The hardware architecture is selected by SWITCH_TYPE on
Switch architecture selector – openenoc_eth_switch at elaboration, independently of the runtime operation
mode exposed here.