RTL Reference

This chapter describes RTL block responsibilities, interfaces, and behavior. Each block description identifies the implemented functionality and the design requirements that remain to be implemented.

The reference covers every project module and interface under hw/rtl, alongside the generated HAL interfaces, CSR modules, and packages. Each block has its own RTL Reference page, named after its SV source. Each page begins with a brief component description, followed by parameter and signal tables and architecture and operation. Handwritten runtime blocks and interfaces also include functional scenarios. Parameter tables include defaults and allowed values; signal tables include types and directions or modport roles. Packages list generated constants and have no runtime signals.

Components with a dedicated DV suite describe only their own testbench and coverage in a Verification section after the functional scenarios, while the suite README files provide configuration and test-running instructions. The shared verification framework is described in Verification Infrastructure; third-party TAXI and PicoRV32 sources remain dependencies.

Interfaces

• Native CPUIF – openenoc_cpuif_if
• Bidirectional Ethernet link – openenoc_eth_if
• Forwarding lookup – openenoc_lookup_if
• Forwarding learning – openenoc_learning_if
• Endpoint peer lookup – openenoc_peer_lookup_if
• IRQ event producer – openenoc_irq_event_if
• DMA and RMEM Transfer Interface – openenoc_dma_transfer_if

Endpoint blocks

• Endpoint interface – openenoc_endpoint_interface
• Direct AXIS over CSR – openenoc_endpoint_direct_axis
• Peer-table lookup – openenoc_endpoint_peer_lookup
• IRQ controller – openenoc_endpoint_irq_controller
• DMA Engine – openenoc_endpoint_dma_engine
• oETP Engine – openenoc_endpoint_oetp_engine

Switching and stream transport

• Ethernet clock/width adapter – openenoc_eth_adapter
• Switch architecture selector – openenoc_eth_switch
• Shared-bus switch – openenoc_eth_switch_shared_bus
• Crossbar switch – openenoc_eth_switch_crossbar
• Forwarding table – openenoc_forwarding_table
• Forwarding-table request arbiter – openenoc_forwarding_table_arb_mux
• Header parser – openenoc_axis_header_parser
• Forwarding engine – openenoc_axis_forwarding_engine
• Stream demultiplexer – openenoc_axis_demux
• Stream switch – openenoc_axis_switch
• Stream monitor – openenoc_axis_monitor

Memory interconnect and processor

• AXI4-Lite to CPUIF – openenoc_axil_cpuif_adapter
• CPUIF to AXI4-Lite – openenoc_cpuif_axil_adapter
• AXI4-Lite crossbar – openenoc_axil_crossbar
• Address decoder – openenoc_axil_crossbar_addr
• Crossbar read path – openenoc_axil_crossbar_rd
• Crossbar write path – openenoc_axil_crossbar_wr
• Crossbar elastic buffer – openenoc_axil_crossbar_skid_buffer
• AXI4-Lite RAM – openenoc_axil_ram
• PicoRV32 wrapper – openenoc_picorv32
• PicoRV32 AXI4-Lite adapter – openenoc_picorv32_axil_adapter
• Round-robin arbiter – openenoc_rr_arbiter

Generated HAL RTL

SystemRDL is the source of truth for generated interfaces, register blocks, bridges, and endpoint packages. make -C hal all regenerates these artifacts. RTL changes belong in the RDL, exporter, or template; generated SV is not edited by hand. The software-visible register specification remains in HAL Architecture Specification.

• Endpoint CSR/core interface – openenoc_endpoint_if
• Switch CSR/core interface – openenoc_switch_if
• Full endpoint register block – openenoc_endpoint_full_csr
• Full endpoint CSR bridge – openenoc_endpoint_full_csr_bridge
• CSR types package – openenoc_endpoint_full_csr_pkg
• Endpoint configuration package – openenoc_endpoint_full_pkg

hal/tools/ unit tests cover the exporters; dv/hal/openenoc_endpoint_full/ checks the generated CSR model against RTL, and endpoint tests cover wiring.

Endpoints

• Full endpoint – openenoc_endpoint_full