Endpoint CSR/core interface – openenoc_endpoint_if
Defines the structured control and status boundary between endpoint hardware and its register bank.
Source: openenoc_endpoint_if.sv.
RDL: openenoc_endpoint_interface.rdl.
Parameters
Name |
Default value |
Allowed values |
Description |
|---|---|---|---|
|
|
Integer >= 1, in 32-bit words |
Size of the external scalar-memory aperture. |
|
|
Integer >= 1; match generated CSR array |
Number of peer-table entries. |
Signals
Directions are relative to the named modport. The monitor modport, where present, observes signals as inputs and does not drive them.
Name |
Type |
Direction / role |
Description |
|---|---|---|---|
|
|
input |
Clock for this component or interface domain. |
|
|
input |
Active-high reset of transaction and control state. |
|
|
csr: input; core: output |
Hardware status, next-value updates, acknowledgements, and command clears. |
|
|
csr: output; core: input |
Stored software configuration, pending commands, and external register requests. |
Architecture and operation
The interface provides csr_to_core and core_to_csr structured signals,
with csr and core modports. Parameters RMEM_TOTAL_DEPTH and
NUM_OF_PEERS set the external RMEM aperture and peer array. The RMEM
byte-address width is derived from the aperture size. The interface carries
configuration, direct/raw DMA controls, IRQ state, peer fields, and the external
RMEM request/ACK/read-data boundary. clk/rst belong to the endpoint domain.
Each connected core block owns its assigned fields.
CSR field |
Codes |
Meaning |
|---|---|---|
|
0..7 |
Raw transmit result: |
|
0..7 |
Raw receive result: |
|
0..15 |
Shared peer DMA/RMEM result, including timeout and remote failures. |
The complete value-to-mnemonic mapping is in
Error reporting. The corresponding source constants use
the ERROR_ prefix; diagrams omit that prefix. A clear error flag and
NONE describe no recorded failure, independently of idle/done state.
IRQ source encodings are listed in IRQ event producer – openenoc_irq_event_if.